Reconfigurable Power Efficient High Throughput Digital System

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R. N. Patil S. Subbaraman

Abstract

In various real-time applications, such as Computer Graphics, Virtual Reality, System Control, Digital Signal Processing etc., a sequence of data sets needs to be processed by multiple functional units either sequentially using pipeline architecture or in parallel using parallel architectures or both sequentially and in parallel in case of mixed type of architectures. Power reduction in electronic systems has always been one of the important considerations. Similarly the demand for real time processing of many complex algorithms as required by state-of-the-art DSP applications has put stress on capability of electronic systems to handle high input data rates resulting into high throughput systems. This paper deals with designing a dynamic frequency scaling enabled platform for power efficient and high throughput digital system in multiprocessing environment, and its implementation in FPGA. The dynamic frequency scaling unit reconfigures the main clock of FPGA according to the processing ability or the volume of the data to be processed by individual subsystems of a multiprocessing system. The effect of this on energy saving and throughput of the multiprocessing system are evaluated in the context of image processing by implementing few image processing algorithms such as contrast stretching, Sobel Filter, Image Thresholding, Gaussian Filter. The details of the concept, implementation and the results thereof are presented here.
 

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How to Cite
PATIL, R. N.; SUBBARAMAN, S.. Reconfigurable Power Efficient High Throughput Digital System. ASIAN JOURNAL OF CONVERGENCE IN TECHNOLOGY, [S.l.], v. 3, n. 3, aug. 2017. ISSN 2350-1146. Available at: <http://asianssr.org/index.php/ajct/article/view/2753>. Date accessed: 21 oct. 2017.
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