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This paper presents high speed radix 8 CORDIC processor. Overall latency to estimate sine and cosine reduces 38% compared to that of radix 4 CORDIC processor. But hardware overhead increases due to additional adders and shifters required. The proposed design has been coded in Verilog and synthesized using Cadence RTL Encounter. PDP, EDP, and ADP parameters are estimated for radix 8 CORDIC processor and results are compared with respect to radix 4 CORDIC processor.