Quality of Service for Improving the Performance of Network-On-Chip : A Review

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Jaya R. Surywanshi Dr. Dinesh V. Padole


SoCs typically consist of several intellectual IP blocks like accelerators imaging, video decoders, graphics, etc. including with general purpose cores . In this large heterogeneous architecture, the requirements placed by the processing on the core versus the processing on the IP block. Traditionally, bus mechanism is preferred for communication to all devices presents on it. Existing on-chip interconnection networks are usually implemented using buses. Bus-based mechanism is preferred for interconnection in SoC such as Avalon, AMBA, CoreConnect, STBus, Wishbone etc. buses are used in SoC architectures to share resources . Bus based mechanism have several interconnect issues that have direct impact on the performance of SoC. Thats why new mechanism are required for better performance as well improving the QoS of SoC . The enactment of NoC as the communication system for complex integrated systems and has been promoted by the increasing number of processing elements integrated in current MPSoCs. Quality-of-Service becomes a vital requirement in SoCs with NoCs. The Quality of Service NoC presents a preferment solution that provides high throughput and low latency transfers. Researchers have introduced different methods and techniques to support QoS. This paper presents a review on the existing work done by different authors on QoS parameters which tries to improve the performance of the NoC.

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SURYWANSHI, Jaya R.; PADOLE, Dr. Dinesh V.. Quality of Service for Improving the Performance of Network-On-Chip : A Review. ASIAN JOURNAL OF CONVERGENCE IN TECHNOLOGY, [S.l.], v. 3, n. 3, aug. 2017. ISSN 2350-1146. Available at: <http://asianssr.org/index.php/ajct/article/view/2855>. Date accessed: 21 oct. 2017.