TY - JOUR AU - Siddhesh Bhasale PY - 2018/04/15 Y2 - 2024/03/29 TI - DESIGN AND TESTING OF MULTIPLIER CIRCUIT USING BIST FOR FPGA JF - Asian Journal For Convergence In Technology (AJCT) ISSN -2350-1146 JA - AJCT VL - 4 IS - I SE - Electronics and Telecommunication DO - UR - http://asianssr.org/index.php/ajct/article/view/498 AB - The intricacies of IC (Integrated circuits) are increasing at a swift pace, Thus testing these ICs for erogenous faults has become very important. BIST is very popular testing mechanism which involves the design of test circuitry around a system that automatically tests the system by applying certain test stimulus and observing the system response generated due to the stimulus of the applied testing patterns. In BIST, the framework for testing the circuit is integrated in the system hardware, As a result the testing process becomes fast and cheaper than using ATE (Automatic test Equipment). Multipliers are basic building blocks of electronic design, they are extensively used in processors, microcontrollers, computers etc for signal processing. The self testing ability of a multiplier is an improvement compared to a basic multiplier design. This feature enables on-field testing of the multipliers without the use of costly ATEs. The BIST (built-in-self-test) functionality gives a brief analysis of the hardware faults that may be present in the multiplier. This paper puts forward a implementation of a multiplier with BIST functionality. Using BIST the multiplier is checked for various stuck at faults. Xilinx Vivado tool is used for modeling of this multiplier. For the design of self-test circuit, TPG (Test Pattern Generator) is used. ER -