System Level Modeling and Simulation of Built-in-Self-Test Enable Oversampling Analog-to-Digital Converter
Abstract
System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). SystemC is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.
References
[2] Lee, Kuen-Jong, Soon-Jyh Chang, and Ruei-Shiuan Tzeng. "A sigma-delta modulation based BIST scheme for A/D converters." In Test Symposium, 2003. ATS 2003. 12th Asian, pp. 124-127. IEEE, 2003.
[3] Chouba, Nabil, and Laroussi Bouzaida. "A BIST architecture for sigma delta ADC testing based on embedded NOEB self-test and CORDIC algorithm." InDesign and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, pp. 1-7. IEEE, 2010.
[4] Damarla, Raju T., Wei Su, Moon J. Chung, Charles E. Stroud, and Gerald T. Michael. "A built-in self test scheme for VLSI." In Design Automation Conference, 1995. Proceedings of the ASP-DAC'95/CHDL'95/VLSI'95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal, pp. 217-222. IEEE, 1995.
[5] Hawrysh, Evan M., and Gordon W. Roberts. "An integration of memory-based analog signal generation into current DFT architectures." In Test Conference, 1996. Proceedings., International, pp. 528-537. IEEE, 1996.
[6] Huang, Jiun-Lang, Chee-Kian Ong, and Kwang-Ting Cheng. "A BIST scheme for on-chip ADC and DAC testing." In Proceedings of the conference on Design, automation and test in Europe, pp. 216-220. ACM, 2000.
[7] Xing, Hanqing, Hanjun Jiang, Degang Chen, and Randall L. Geiger. "High-resolution ADC linearity testing using a fully digital-compatible BIST strategy." Instrumentation and Measurement, IEEE Transactions on 58, no. 8 (2009): 2697-2705.
[8] Duan, Jingbo, Degang Chen, and Randall Geiger. "Cost effective signal generators for ADC BIST." In Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp. 13-16. IEEE, 2009.
[9] Huang, Jiun-Lang, and Kwang-Ting Cheng. "Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis." In Test Conference, 2000. Proceedings. International, pp. 1021-1030. IEEE, 2000..
[10] Wen, Yun-Che, and Kuen-Jong Lee. "An on chip ADC test structure." In Proceedings of the conference on Design, automation and test in Europe, pp. 221-225. ACM, 2000..
[11] Liang, Sheng-Chuan, and Hao-Chiao Hong. "A Digitally Testable Modulator Using the Decorrelating Design-for-Digital-Testability." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 19, no. 3 (2011): 503-507.
[12] Dubois, Matthieu, Haralampos-G. Stratigopoulos, and Salvador Mir. "Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs." In Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2012 18th International, pp. 5-10. IEEE, 2012.
[13] Ong, Chee-Kian, Kwang-Ting Cheng, and Li-C. Wang. "A new sigma-delta modulator architecture for testing using digital stimulus." Circuits and Systems I: Regular Papers, IEEE Transactions on 51, no. 1 (2004): 206-213..
[14] Dufort, Benoit, and Gordon W. Roberts. "On-chip analog signal generation for mixed-signal built-in self-test." Solid-State Circuits, IEEE Journal of 34, no. 3 (1999): 318-330.
[15] Kook, Sehun, Alfred Gomes, Le Jin, David Wheelright, and Abhijit Chatterjee. "Optimal Linearity Testing of Sigma-Delta Based Incremental ADCs Using Restricted Code Measurements." In Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2011 IEEE 17th International, pp. 72-77. IEEE, 2011.
[16] Hung, Shao-Feng, and Hao-Chiao Hong. "A Fully Integrated BIST ADC Using the In-Phase and Quadrature Waves Fitting Procedure." Instrumentation and Measurement, IEEE Transactions on 63, no. 12 (2014): 2750-2760.
[17] Ahmad, Shakeel, and Jerzy Døbrowski. "On-chip spectral test for high-speed ADCs by ΣΔ technique." In Circuit Theory and Design (ECCTD), 2011 20th European Conference on, pp. 661-664. IEEE, 2011.
[18] Yong-sheng, Wang, Wang Jin-xiang, Lai Feng-chang, and Ye Yi-zheng. "A low-cost BIST scheme for ADC testing." In ASIC, 2005. ASICON 2005. 6th International Conference On, vol. 2, pp. 694-698. IEEE, 2005.
[19] Mir, Salvador. "A SNDR BIST for\ Sigma\ Delta Analogue-to-Digital Converters." In null, pp. 314-319. IEEE, 2006.
[20] Bandopadyay, T. K., Manish Saxena, and Raghav Shrivastava. "Sigma Delta Modulator with Improved Performance through Evolutionary Algorithm." International Journal of Science and Research (IJSR) Volume 2 Issue 3, March 2013.
[21] Benabes, Philippe. "Accurate time-domain simulation of continuous-time sigma–delta modulators." Circuits and Systems I: Regular Papers, IEEE Transactions on 56.10 (2009): 2248-2258.
[22] C. H. E. N. Zhicai, Mathew Bond, and Nijad Anabtawi. "Design of a Second Order Continuous Time Sigma Delta Modulator with Improved Dynamic Range." Final Project of Oversampling Class, Fall 2007 Arizona State University.
[23] Hart, Adam, and Sorin P. Voinigescu. "A 1 GHz Bandwidth Low-Pass ADC With 20–50 GHz Adjustable Sampling Rate." Solid-State Circuits, IEEE Journal of 44.5 (2009):
[24] Toner, Michael F., and Gordon W. Roberts. "A BIST Scheme for an SNR Test of a Sigma-Delta ADC." Test Conference, 1993. Proceedings., International. IEEE, 1993.
[25] Rolindez, Luis, "A SNDR BIST for/spl Sigma//spl Delta/analogue-to-digital converters." VLSI Test Symposium, 2006. Proceedings. 24th IEEE. IEEE, 2006.
[26] Prateek Verma, Anil Kumar Sahu ,Dr. Vivek Kumar Chandra, Dr. G.R.Sinha. A Graphical User Interface Implementation of Second Order Sigma- Delta Analog to Digital Converter with Improved Performance Parameters, International Journal For Research In Applied Science And Engineering Technology ,Vol. 2 Issue VII, July 2014.
[27] Sahu, Anil Kumar, Vivek Kumar Chandra, and G. R. Sinha. "System Level Behavioral Modeling of CORDIC Based ORA of Built-in-Self-Test for Sigma-Delta Analog-to-Digital Converter." International Journal of Signal and Image Processing Issues 2015, no. 2 (2016).
[28] Sahu, Anil Kumar, Chandra, Vivek Kumar, et. Sinha, G. R. “A Review on System Level Behavioral Modeling and Post Simulation of Builtin-Self-Test of Sigma-Delta Modulator Analog-to-Digital Converter”International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3 no. 2, pp. 206-209.
[29] Sahu, Anil Kumar, Chandra, Vivek Kumar, et SINHA, G. R. “Improved SNR and ENOB of SigmaDelta Modulator for Post Simulation and High Level Modeling of Built-in-Self Test Scheme.” 2015 International Journal of Computer Applications (0975 – 8887) Applications of Computers and Electronics for the Welfare of Rural Masses (ACEWRM) 2015, pp. 11-14.
[30] Fitzgibbon Brain, Michal Peter Kennedy, and Franco Maloberti, "Hardware Reduction In Digital Delta Modulator Via Bus -Splitting and Error Masking-Part Ii:Non constant Input," IEEE transactions On Circuit And Systems, vol. 59, no. 9, pp. 1980-1991, September 2012.
[31] Fitzgibbon Brain, Michal Peter Kennedy, and Franco Maloberti, "Hardware Reduction In Digital Delta Modulator Via Bus -Splitting and Error Masking-Part Ii:Non constant Input," IEEE transactions On Circuit And Systems, vol. 59, no. 9, pp. 1980-1991, September 2012.
[32] Philipee Benabes and catalin Adrian Tugui, "Effective Modeling of CT Functions For Fast simulation Using MATALB/SIMULINK And VHD -AMS Applied to Sigma Delta Architectures," IEEE Conference on communication system and Networking Technology, pp. 2269-2272, 2011.
[33] Drago Strle and Janez Trontelj, "High Level Simulation of Real Time BIST of Sigma Delta A/D Converters," International Conference on Synthesis ,Modelling ,Analysis And Simulation Method And applictaion To Circuit Design , pp. 285-289, 2012.
[34] Hao Chiao Hong, Sheng Chaun Liang, and Hong Chin Song, "A Built in Self-Test Sigma Delat ADC Prototype," J. Electon Test, vol. 25, pp. 145-156, 2009.
[35] Sheikh Saine, Julian Raczkowycz, and Peter Mather, "An Analogue Test Response Compaction Techinque Using Delta -Sigma Modulation ," Microelectonics Journal , vol. 32, pp. 339-350, 2001.
To ensure uniformity of treatment among all contributors, other forms may not be substituted for this form, nor may any wording of the form be changed. This form is intended for original material submitted to AJCT and must accompany any such material in order to be published by AJCT. Please read the form carefully.
The undersigned hereby assigns to the Asian Journal of Convergence in Technology Issues ("AJCT") all rights under copyright that may exist in and to the above Work, any revised or expanded derivative works submitted to AJCT by the undersigned based on the Work, and any associated written, audio and/or visual presentations or other enhancements accompanying the Work. The undersigned hereby warrants that the Work is original and that he/she is the author of the Work; to the extent the Work incorporates text passages, figures, data or other material from the works of others, the undersigned has obtained any necessary permission. See Retained Rights, below.
AUTHOR RESPONSIBILITIES
AJCT distributes its technical publications throughout the world and wants to ensure that the material submitted to its publications is properly available to the readership of those publications. Authors must ensure that The Work is their own and is original. It is the responsibility of the authors, not AJCT, to determine whether disclosure of their material requires the prior consent of other parties and, if so, to obtain it.
RETAINED RIGHTS/TERMS AND CONDITIONS
1. Authors/employers retain all proprietary rights in any process, procedure, or article of manufacture described in the Work.
2. Authors/employers may reproduce or authorize others to reproduce The Work and for the author's personal use or for company or organizational use, provided that the source and any AJCT copyright notice are indicated, the copies are not used in any way that implies AJCT endorsement of a product or service of any employer, and the copies themselves are not offered for sale.
3. Authors/employers may make limited distribution of all or portions of the Work prior to publication if they inform AJCT in advance of the nature and extent of such limited distribution.
4. For all uses not covered by items 2 and 3, authors/employers must request permission from AJCT.
5. Although authors are permitted to re-use all or portions of the Work in other works, this does not include granting third-party requests for reprinting, republishing, or other types of re-use.
INFORMATION FOR AUTHORS
AJCT Copyright Ownership
It is the formal policy of AJCT to own the copyrights to all copyrightable material in its technical publications and to the individual contributions contained therein, in order to protect the interests of AJCT, its authors and their employers, and, at the same time, to facilitate the appropriate re-use of this material by others.
Author/Employer Rights
If you are employed and prepared the Work on a subject within the scope of your employment, the copyright in the Work belongs to your employer as a work-for-hire. In that case, AJCT assumes that when you sign this Form, you are authorized to do so by your employer and that your employer has consented to the transfer of copyright, to the representation and warranty of publication rights, and to all other terms and conditions of this Form. If such authorization and consent has not been given to you, an authorized representative of your employer should sign this Form as the Author.
Reprint/Republication Policy
AJCT requires that the consent of the first-named author and employer be sought as a condition to granting reprint or republication rights to others or for permitting use of a Work for promotion or marketing purposes.
GENERAL TERMS
1. The undersigned represents that he/she has the power and authority to make and execute this assignment.
2. The undersigned agrees to indemnify and hold harmless AJCT from any damage or expense that may arise in the event of a breach of any of the warranties set forth above.
3. In the event the above work is accepted and published by AJCT and consequently withdrawn by the author(s), the foregoing copyright transfer shall become null and void and all materials embodying the Work submitted to AJCT will be destroyed.
4. For jointly authored Works, all joint authors should sign, or one of the authors should sign as authorized agent
for the others.
Licenced by :
Creative Commons Attribution 4.0 International License.
