High Performance Arithmetic and Logic Unit with Enhanced MTCMOS and Transistor Stacking Techniques

  • Esther Rani Thuraka
Keywords: Short Channel; Leakage Power; MTCMOS; EMTCMOS; Transistor Stacking, Arithmetic and Logic Unit;


Short channel devices need lower power supply voltages to reduce power consumption. This forces a reduction in the threshold voltage that causes a substantial increase of weak inversion current. The popular leakage control technique is Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technique. Power gating uses a pMOS transistor and/or an nMOS transistor to disconnect supply voltage from the logic when the logic is inactive by creating virtual VDD and Ground. This technique can decrease leakage power by more than 50% with negligible delay. For further reduction in the leakage power in deep submicron, a technique known as Enhanced MTCMOS (EMTCMOS) is used which uses a stack of NMOS and PMOS transistors as used in case of MTCMOS technique. EMTCMOS technique condenses leakage further, over the conventional MTCMOS circuits. Transistor stacking is another technique that is verified for leakage power reduction. An Arithmetic and Logic Unit is designed using CMOS, MTCMOS, EMTCMOS and Transistor stacking techniques and compared for the leakage power reduction


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How to Cite
Thuraka, E. R. (2018, April 15). High Performance Arithmetic and Logic Unit with Enhanced MTCMOS and Transistor Stacking Techniques. ASIAN JOURNAL FOR CONVERGENCE IN TECHNOLOGY (AJCT ) -UGC LISTED, 4(I). Retrieved from http://asianssr.org/index.php/ajct/article/view/453
Electrical & Electronics Engineering