DESIGN AND TESTING OF MULTIPLIER CIRCUIT USING BIST FOR FPGA
The intricacies of IC (Integrated circuits) are increasing at a swift pace, Thus testing these ICs for erogenous faults has become very important. BIST is very popular testing mechanism which involves the design of test circuitry around a system that automatically tests the system by applying certain test stimulus and observing the system response generated due to the stimulus of the applied testing patterns. In BIST, the framework for testing the circuit is integrated in the system hardware, As a result the testing process becomes fast and cheaper than using ATE (Automatic test Equipment). Multipliers are basic building blocks of electronic design, they are extensively used in processors, microcontrollers, computers etc for signal processing. The self testing ability of a multiplier is an improvement compared to a basic multiplier design. This feature enables on-field testing of the multipliers without the use of costly ATEs. The BIST (built-in-self-test) functionality gives a brief analysis of the hardware faults that may be present in the multiplier. This paper puts forward a implementation of a multiplier with BIST functionality. Using BIST the multiplier is checked for various stuck at faults. Xilinx Vivado tool is used for modeling of this multiplier. For the design of self-test circuit, TPG (Test Pattern Generator) is used.
LOGIC CIRCUITS USING BUILT IN SELF TEST SCHEME FOR FPGAs” 2015 Fifth International Conference on Communication Systems and Network Technologies
[2Bharti Mishra , Dr. Rita Jain and Prof. Richa Saraswat ” Low Power BIST based Multiplier Design and Simulation using FPGA “,2016 IEEE Students' Conference on Electrical, Electronics and Computer Science
 Nishant Govindrao Pandharpurkar* and V. Ravi “ Design of BIST using Self-Checking Circuits for Multipliers” Indian Journal of Science and Technology, Vol 8(19), DOI:10.17485/ijst/2015/v8i19/77006, August 2015
 M.H. Husin, S.Y. Leong, M.F.M. Sabri, R. Nordiana “Built in self test for RAM Using VHDL “2012 IEEE Colloquium on Humanities, Science & Engineering Research (CHUSER 2012), December 3-4, 2012, Kota Kinabalu, Sabah, Malaysia 272
 Designing of BIST Architecture of Generic Multipliers.Anju Rajput, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 5, Ver. II (Sep-Oct. 2014)
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