Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing
This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length.
Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU.
The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.
 Ruchi anchaliya, Chiranjeevi G N, Subhash Kulkarni,” Efficeint Computing Techniques using Vedic Mathematicas Sutras”, international journal of innovative research in electrical, Electronics, Instrumentation and Control engineering, volume 3,Issues 5, May 2015
 Himanshu Thapliyal, Saurabh Kotiyal and M. B Srinivas, “Design and Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics”, Centre for VLSI and Embedded System Technologies, International Institute of Information Technology, Hyderabad, 500019, India, 2005 IEEE
 Vaijyanath Kunchigi, linganagouda kulkarni and subhash kulkarni 32-bit MAC unit design using Vedic multiplier – published at: “International Journal of Scientific and Research Publications (IJSRP), Volume 3, Issue2, February 2013 Edition”.
 Sumita Vaidya and Deepak Dandekar, “Delay- Power Performance comparison of Multipliers in VLSI Circuit Design”, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010.
 Umesh Akare, T.V. More and R.S. Lonkar, “Performance Evaluation and Synthesis of Vedic Multiplier”, National Conference on Innovative Paradigms in Engineering & Technology (NCIPET- 2012), proceedings.
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