Effective Low Power Testing strategy with respect to Built in Self-Test(BIST): A Survey
Abstract
Low-power VLSI circuits are indispensable for modern electronic devices, and numerous hardware/softwarebased techniques have been developed for drastically reducing functional power dissipation. However, testing such low-power devices has increasingly become a severe challenge, especially in at-speed scan testing. The reason is that functional constraints with respect to circuit operations and clocking are mostly ignored in at-speed scan testing, which may result in test power that is 3X to 8X higher than functional power. This paper presents different low power techniques which can be applied to reducing the test power of Built in Self Test (BIST) circuits used for various digital IC’s.
References
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