Architectural Design Of Instruction List Processor For Process Control

  • Dheeraj Umakant Kore University of Pune
  • Rahul A Pagare


In this paper an architecture of Instruction List (IL) processor is designed for process control according to the norm of IEC 61131-3. Increasing complexity in process control and safety critical application require fast output response. In order to improve execution speed of process control operation controller generates fast output response. The PLC (Programmable Logic Controller) is device that automates the process control operation. The designed processor exhibits desired performance much higher than current commercial PLCs. The architecture is to be implemented on FPGA platform for verification purpose. The proposed architecture is to be specified fully in VHDL and is designed to emulate the functionality of IL Processor in terms of instruction set fetching, decoding, executing, operand addressing and bus operation. To validate the advance of the proposed architecture, two ladder programs are compiled to the instruction set of proposed IL processor as well as in IL programming language.

Keywords: Architecture, Instruction, List(IL), VHDL, FPGA, IEC61131-3, PLC


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How to Cite
Kore, D., & Pagare, R. (2017). Architectural Design Of Instruction List Processor For Process Control. Asian Journal For Convergence In Technology (AJCT), 1(1`), 5. Retrieved from