Architectural Design Of Instruction List Processor For Process Control
In this paper an architecture of Instruction List (IL) processor is designed for process control according to the norm of IEC 61131-3. Increasing complexity in process control and safety critical application require fast output response. In order to improve execution speed of process control operation controller generates fast output response. The PLC (Programmable Logic Controller) is device that automates the process control operation. The designed processor exhibits desired performance much higher than current commercial PLCs. The architecture is to be implemented on FPGA platform for verification purpose. The proposed architecture is to be specified fully in VHDL and is designed to emulate the functionality of IL Processor in terms of instruction set fetching, decoding, executing, operand addressing and bus operation. To validate the advance of the proposed architecture, two ladder programs are compiled to the instruction set of proposed IL processor as well as in IL programming language.
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 Mrs. Shilpa Rudrawar and Prof. Manish M. Patil, “Design of instruction list (IL) processor for process control’ In Proceedings of International Journal of Electronics and Computer Science Engineering V1N3-1734-1742,India 2012
 IEC 61131 Ageneral overview & emerginh trends IEEE INDUSTRIAL ELECTRONICS MAGAZINE 1932-4529/09/$26.00&2009 IEEE
 Shuting-zeng , Zhijia-yang, “High performance architecture design of PLC dedicated processor” Industrial informatics laboratoryShenyang institute of automation, Graduate School of the Chinese Academy of Sciences Shenyang, China 2010 IEEE.
 Spartan-3 Generation FPGA User Guide UG331 (v1.8) June 13, 2011
 Snaider Carrillo L., Agenor Polo Z. , Mario Esmeral P."Design and Implementation of an Embedded Microprocessor Compatible WithIL Language in Accordance to the Norm IEC 61131-3", Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005) 0-7695-2456-7/05-$20.00 © 2005 IEEE.
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